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Lab 2 Tips
For Lab 2, there are a few tips to finishing the lab with ease. A lot of the tips have to do with how you create your schematics and layout your gates. Follow these tips to ease your life and learn good project skills for the future. KEY TO EASE: Be anal and make your schematics clean and neat - this in turn allows you to debug your schematics with ease. Click here for a TXT version of the notes. Macros and Symbols: - Get used to making macros out of or symbolizing your combinational logic or your state machines. It will make things cleaner and easier to use - However, don't get to happy with using macros. The key in using macros is to help divide your project/lab into sub-circuits, modules, sub-logic, etc. Don't try to symbolize or macro everything you have. There is no point in creating a macro for one logic gate unless stated by us or the lab. - NOTE: In this lab, you should only need to create a total of 4 different macros. 2 of the macros are VERY simple. - All Macros/Symbols need input and output terminals or input or output bus terminals. Wiring and Terminals: - Avoid running branching wires for a signal that is used for multiple inputs - Use the naming technique of the wires to connect an output or signal to an input. - Click here for an example of the naming technique. Wiring Buses: - Tap the bus line by naming input wires by the name of the bus line and the specified "bit" wanted. - If the bus line was labeled A[2:0], by naming an input wire A1, it will implicitly connect the bus lines second "bit" to that wire. - As with wires, when symoblizing or making macros, you need bus terminals to have an input or output buses coming from your symbol or macro. - Click here for an example of wiring buses. Simulation: - When simulating, make sure the current sheet you want to simulate is part of the project and does not say "Non-Project". It must be part of the project. - Usually accessing the simulator will create and export the netlist of your current sheet automatically. However, it is always more reliable to Options->Integrity Test, Options->Create Netlist, and Options->Export Netlist.. from the menu bar. - When simulating, only one sheet should be a project. Other sheets should either be removed frome the project, or made into macros for the single high-level sheet in the project. Multiple project sheets may cause bad simulation of the logic or even conflicts. - Click
here for an example of what is WRONG. Other Stuff: - Xilinx can be very quirky at times and sometimes everything is right but it doesn't seem to work. Here are some stupid tips but they do help solve 50% of the problems. - REBOOT or RESTART the software. - Move to a different computer. - Rebuild your macros or your schematics. |
